NXP Semiconductors /MIMXRT1052 /USDHC1 /VEND_SPEC

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Interpret as VEND_SPEC

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (VSELECT_0)VSELECT 0 (CONFLICT_CHK_EN_0)CONFLICT_CHK_EN 0 (AC12_WR_CHKBUSY_EN_0)AC12_WR_CHKBUSY_EN 0 (FRC_SDCLK_ON_0)FRC_SDCLK_ON 0 (CRC_CHK_DIS_0)CRC_CHK_DIS 0 (CMD_BYTE_EN_0)CMD_BYTE_EN

CRC_CHK_DIS=CRC_CHK_DIS_0, CONFLICT_CHK_EN=CONFLICT_CHK_EN_0, CMD_BYTE_EN=CMD_BYTE_EN_0, FRC_SDCLK_ON=FRC_SDCLK_ON_0, AC12_WR_CHKBUSY_EN=AC12_WR_CHKBUSY_EN_0, VSELECT=VSELECT_0

Description

Vendor Specific Register

Fields

VSELECT

Voltage Selection

0 (VSELECT_0): Change the voltage to high voltage range, around 3.0 V

1 (VSELECT_1): Change the voltage to low voltage range, around 1.8 V

CONFLICT_CHK_EN

Conflict check enable.

0 (CONFLICT_CHK_EN_0): Conflict check disable

1 (CONFLICT_CHK_EN_1): Conflict check enable

AC12_WR_CHKBUSY_EN

AC12_WR_CHKBUSY_EN

0 (AC12_WR_CHKBUSY_EN_0): Do not check busy after auto CMD12 for write data packet

1 (AC12_WR_CHKBUSY_EN_1): Check busy after auto CMD12 for write data packet

FRC_SDCLK_ON

FRC_SDCLK_ON

0 (FRC_SDCLK_ON_0): CLK active or inactive is fully controlled by the hardware.

1 (FRC_SDCLK_ON_1): Force CLK active.

CRC_CHK_DIS

CRC Check Disable

0 (CRC_CHK_DIS_0): Check CRC16 for every read data packet and check CRC bits for every write data packet

1 (CRC_CHK_DIS_1): Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet

CMD_BYTE_EN

CMD_BYTE_EN

0 (CMD_BYTE_EN_0): Disable

1 (CMD_BYTE_EN_1): Enable

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